Аннотация:A 32/spl times/32 bit multiplier has been designed using dynamic differential logic improved for low voltage operation. Booth 4 encoding has been used to achieve high speed and small area. Using a 0.35 /spl mu/m CMOS process with Vth=0 V for 0.5 V operation, the estimated delay and power dissipation are 7 ns and 20 mW at 100 MHz. A test chip fabricated in a standard double-metal 0.8 /spl mu/m CMOS process with Vth=0.8 V for 5 V operation achieved 13 ns speed and 1.05 W power dissipation at 75 MHz.
