Grooved-gate structure metal-oxide-semiconductor (MOS) device is considered as a more promising candidate used in deep-sub-micron region for the improvement of reliability. In this paper, grooved-gate CMOS devices in the 0.1 /spl mu/m regime have been studied by both experiments and simulations. Compared with the conventional planar devices, grooved-gate CMOS shows little threshold voltage roll-off, less short channel effects, but the optimization of the structure and technology is important to obtain high drive current.