A process that enables good gate-oxide integrity (GOI) in W/barrier/poly-Si gates and thermally stable low-resistivity source/drain (S/D) CoSi/sub 2/ electrodes has been developed for high-speed logic circuits with large-scale embedded DRAMs that use Ta/sub 2/O/sub 5/ high-k capacitors for high-density memory cells. Spin-on-glass (SOG)-based films were used to fill in narrow spaces between wordlines, and were also directly formed on silicide films. We prevented the oxidation of silicide during the SOG-based interlayer dielectric (ILD) formation. By using these CoSi/sub 2/ electrodes, we were able to obtain contact resistance ten times lower than that of conventional non-silicide electrodes.