In recent years, the volume of thinned silicon and bumped silicon wafers have increased dramatically. The push to thinner silicon is driven by smart cards and stacked dice for low profile products which are highly popular in the marketplace. The dicing of advanced materials including thin wafers, ultra-thin silicon wafers, wafer with low k dielectric, bonded wafers and cavitated wafers is critically important for high volume IC production. Today, mechanical dicing with diamond saw blades remains the most cost effective manufacturing process. Advances in dicing processes and blade design allow for dicing of these wafers with minimum mechanical damage to the dice. Achieving end cut with no damage requires a fine balance between the design of the saw street dimension, the contents in the street and the wafer level processing that introduces internal stresses into the wafer. With the push to maximize die count per wafer, the saw street is often filled with wafer test features that not only degrade the cutting action of the blade but introduce internal stress in the silicon wafer. Data shows that chipping on redistributed and bumped wafers is higher than non-bumped wafers. This paper shows results from improved dicing parameters that will overcome yield loss during mechanical dicing without having to resort to laser dicing.